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W631GG6KB
17.When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t ERR (mper),act of the input clock, where 2 ≤ m ≤ 12. (output deratings are relative to the actual SDRAM
input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has t ERR (mper),act,min = - 138 pS and
t ERR (mper),act,max = + 155 pS, then
t DQSCK, min(derated) = t DQSCK ,min - t ERR (mper),act,max = - 255 pS - 155 pS = - 410 pS and
t DQSCK ,max(derated) = t DQSCK ,max - t ERR (mper),act,min = 255 pS + 138 pS = + 393 pS.
Similarly, t LZ(DQ) for DDR3-1333 derates to t LZ(DQ) ,min(derated) = - 500 pS - 155 pS = - 655 pS and
t LZ(DQ ),max(derated) = 250 pS + 138 pS = + 388 pS. (Caution on the min/max usage!)
Note that t ERR (mper),act,min is the minimum measured value of t ERR (nper) where 2 ≤ n ≤ 12, and
t ERR (mper),act,max is the maximum measured value of t ERR (nper) where 2 ≤ n ≤ 12.
18.When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t JIT (per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-1333 SDRAM has t CK (avg),act = 1500 pS,
t JIT (per),act,min = - 58 pS and t JIT (per),act,max = + 74 pS, then
t RPRE ,min(derated) = t RPRE ,min + t JIT (per),act,min = 0.9 x t CK (avg),act + t JIT (per),act,min = 0.9 x 1500
pS - 58 pS = + 1292 pS.
Similarly, t QH ,min(derated) = t QH ,min + t JIT (per),act,min = 0.38 x t CK (avg),act + t JIT (per),act,min = 0.38 x
1500 pS - 58 pS = + 512 pS. (Caution on the min/max usage!).
19.WR in clock cycles as programmed in mode register MR0.
20.t WR (min) is defined in nS, for calculation of t WRPDEN it is necessary to round up t WR (min)/t CK (avg) to the
next integer value.
21.The maximum read preamble is bound by t LZ(DQS ) min on the left side and t DQSCK (max) on the right side.
See Figure 24 - “ READ Timing; Clock to Data Strobe relationship ” on page 45.
22.The maximum read postamble is bound by t DQSCK (min) plus t QSH (min) on the left side and t HZ (DQS) max
on the right side. See Figure 24 - “ READ Timing; Clock to Data Strobe relationship ” on page 45.
23.Value is only valid for RON34.
24.Single ended signal parameter.
25.t REFI depends on T OPER .
26.Start of internal write transaction is defined as follows:
For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
27.CKE is allowed to be registered low while operations such as row activation, precharge, auto-precharge
or refresh are in progress, but power down I DD spec will not be applied until finishing those operations.
28.Although CKE is allowed to be registered LOW after a REFRESH command once t REFPDEN (min) is
satisfied, there are cases where additional time such as t XPDLL (min) is also required. See section 8.17.3
“ Power-Down clarifications - Case 2 ” on page 75.
29.Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
30.ODTH4 is measured from ODT first registered high (without a Write command) to ODT first registered
low, or from ODT registered high together with a Write command with burst length 4 to ODT registered
low.
31.ODTH8 is measured from ODT registered high together with a Write command with burst length 8 to
ODT registered low.
32.This parameter applies upon entry and during precharge power down mode with DLL frozen.
Publication Release Date: Dec. 09, 2013
Revision A05
- 147 -
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